1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having penetration electrodes that penetrates through a semiconductor chip.
2. Description of Related Art
In recent years, a semiconductor device of a stacked type is proposed (see Japanese Patent Application Laid-Open No. 2009-10390, for example). The semiconductor device of this type includes a plurality of semiconductor chips stacked one another and electrically connected to one another by penetration electrodes that penetrates through respective semiconductor chip. The semiconductor device of this type enables the semiconductor chips to be mounted on a circuit substrate in high density.
In the stacked semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2009-10390, each of the semiconductor chips is subjected to a test operation by using a plurality of pads 120 (test pads) provided to each of the semiconductor chips before the semiconductor chips are stacked. After the test operation, a first penetration electrode 155 that penetrates through respective semiconductor chip is so formed as to pass through the pad 120 with insulated from the pad 120. After the semiconductor chips are stacked, the first penetration electrode 155 is used as a signal path of a chip selection signal.
In order to perform a test operation to the stacked semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2009-10390 after the semiconductor chips are stacked, test signals should be input and output via penetration electrodes that is used in a normal operation. However, the following problem may arise when the test operation of the stacked semiconductor device is carried out by the above method.
That is, in a stacked semiconductor device in which a plurality of memory chips and a control chip that controls the memory chips are stacked and connected to one another via penetration electrodes, an operation of the memory chips is controlled by the control chip during normal operation. When the memory chips are subjected to the test operation after the memory chips and the control chip are stacked, the test signals to the memory chips are necessary to supply from various internal circuits in the control chip. If a defect is discovered during the test operation, it is difficult to determine whether the memory chips or the control chip is responsible for the defect. Therefore, as for a stacked semiconductor device in which a plurality of semiconductor chips are stacked and connected to one another through penetration electrodes, it is desirable that a penetration electrode dedicated to the test operation be placed to transmit a test signal via a different route from that of the normal operation.
However, if a penetrating electrode for the test operation is provided to the memory chips in addition to penetrating electrodes for the normal operation, an additional chip area is necessary to dispose the penetrating electrodes for the test operation. In addition, interconnection lines in the memory chips are also necessary to transmit the test signals supplied from a plurality of the penetration electrodes for the test operation. As a result, therefore, a chip area of the memory chips inevitably increase in this case.